Electrically programmable and erasable memory array devices using floating gate for the storage of charges thereon are well known in the art. See, for example, U.S. Pat. No. 4,698,787. In such prior art memory design, the source or ground of the memory array is common to all of the cells or a large portion of the total memory cells. Typically, these types of floating gate memory array devices are termed flash-type EPROM or EEPROM, which can only be erased in a block mode, wherein the complete array or a large portion of the array has to be erased at one time. This is because in this prior art type of memory array device, erasure is induced by raising the ground lines to a very high voltage, typically greater than 10 volts. Since the ground line of the memory array cells are common, every cell in the array is erased.
In U.S. Pat. No. 5,029,130, assigned to the present assignee, which is incorporated herein by reference, a novel type of EEPROM or flash EEPROM memory device is disclosed. In that application, the erase operation can be selectively performed on a single row. However, although the erase operation is selectively performed on a single row, there may be undesired disturbance of the adjacent or nearby unselected cells through the common ground line.
In U.S. patent application Ser. No. 682,459, filed on Apr. 9, 1991, which is also assigned to the present assignee and is incorporated herein by reference, another type of EEPROM memory device is disclosed. In that application, the memory array can be erased on a selective row basis. However, similar to the invention disclosed in U.S. Pat. No. 5,029,130 because erasure is accomplished by high voltage, i.e., greater than 10 volts, the high voltage may disturb the adjacent unselected cells due to the common ground line.